Registers in AddressMap abc_soc_top/dlnk/jesdabc3/pipe_phy_1x4lane_map/pipe_phy_VERSA/versa_PMA0/PMA_RXWORD_Q3/PMA_RXWORD_regs

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AddressMap abc_soc_top/dlnk/jesdabc3/pipe_phy_1x4lane_map/pipe_phy_VERSA/versa_PMA0/PMA_RXWORD_Q3/PMA_RXWORD_regs

AddressUnit: 8

Accessible over:
Group NOC.rcs__axi Mem with fixed address

Address	EndAddress	Name	Description
0x00000000		ffe_coeff_set0_0	placeholder
0x00000004		ffe_coeff_set0_1	placeholder
0x00000008		ffe_coeff_set0_2	placeholder
0x0000000c		ffe_coeff_set0_3	placeholder
0x00000010		ffe_coeff_set0_4	placeholder
0x00000014		ffe_coeff_set1_0	placeholder
0x00000018		ffe_coeff_set1_1	placeholder
0x0000001c		ffe_coeff_set1_2	placeholder
0x00000020		ffe_coeff_set1_3	placeholder
0x00000024		ffe_coeff_set1_4	placeholder
0x00000028		ffe_coeff_set2_0	placeholder
0x0000002c		ffe_coeff_set2_1	placeholder
0x00000030		ffe_coeff_set2_2	placeholder
0x00000034		ffe_coeff_set2_3	placeholder
0x00000038		ffe_coeff_set2_4	placeholder
0x0000003c		ffe_coeff_set3_0	placeholder
0x00000040		ffe_coeff_set3_1	placeholder
0x00000044		ffe_coeff_set3_2	placeholder
0x00000048		ffe_coeff_set3_3	placeholder
0x0000004c		ffe_coeff_set3_4	placeholder
0x00000050		ffe_coeff_set4_0	placeholder
0x00000054		ffe_coeff_set4_1	placeholder
0x00000058		ffe_coeff_set4_2	placeholder
0x0000005c		ffe_coeff_set4_3	placeholder
0x00000060		ffe_coeff_set4_4	placeholder
0x00000064		ffe_coeff_set5_0	placeholder
0x00000068		ffe_coeff_set5_1	placeholder
0x0000006c		ffe_coeff_set5_2	placeholder
0x00000070		ffe_coeff_set5_3	placeholder
0x00000074		ffe_coeff_set5_4	placeholder
0x00000078		ffe_coeff_set6_0	placeholder
0x0000007c		ffe_coeff_set6_1	placeholder
0x00000080		ffe_coeff_set6_2	placeholder
0x00000084		ffe_coeff_set6_3	placeholder
0x00000088		ffe_coeff_set6_4	placeholder
0x0000008c		ffe_coeff_set7_0	placeholder
0x00000090		ffe_coeff_set7_1	placeholder
0x00000094		ffe_coeff_set7_2	placeholder
0x00000098		ffe_coeff_set7_3	placeholder
0x0000009c		ffe_coeff_set7_4	placeholder
0x000000a0		ffe_coeff_set8_0	placeholder
0x000000a4		ffe_coeff_set8_1	placeholder
0x000000a8		ffe_coeff_set8_2	placeholder
0x000000ac		ffe_coeff_set8_3	placeholder
0x000000b0		ffe_coeff_set8_4	placeholder
0x000000b4		ffe_coeff_set9_0	placeholder
0x000000b8		ffe_coeff_set9_1	placeholder
0x000000bc		ffe_coeff_set9_2	placeholder
0x000000c0		ffe_coeff_set9_3	placeholder
0x000000c4		ffe_coeff_set9_4	placeholder
0x000000c8	0x000000cb	(Not allocated)
0x000000cc		ffe_coeff_set10_0	placeholder
0x000000d0		ffe_coeff_set10_1	placeholder
0x000000d4		ffe_coeff_set10_2	placeholder
0x000000d8		ffe_coeff_set10_3	placeholder
0x000000dc		ffe_coeff_set10_4	placeholder
0x000000e0		ffe_coeff_set11_0	placeholder
0x000000e4		ffe_coeff_set11_1	placeholder
0x000000e8		ffe_coeff_set11_2	placeholder
0x000000ec		ffe_coeff_set11_3	placeholder
0x000000f0		ffe_coeff_set11_4	placeholder
0x000000f4		ffe_coeff_set12_0	placeholder
0x000000f8		ffe_coeff_set12_1	placeholder
0x000000fc		ffe_coeff_set12_2	placeholder
0x00000100		ffe_coeff_set12_3	placeholder
0x00000104		ffe_coeff_set12_4	placeholder
0x00000108		ffe_coeff_set13_0	placeholder
0x0000010c		ffe_coeff_set13_1	placeholder
0x00000110		ffe_coeff_set13_2	placeholder
0x00000114		ffe_coeff_set13_3	placeholder
0x00000118		ffe_coeff_set13_4	placeholder
0x0000011c		ffe_coeff_set14_0	placeholder
0x00000120		ffe_coeff_set14_1	placeholder
0x00000124		ffe_coeff_set14_2	placeholder
0x00000128		ffe_coeff_set14_3	placeholder
0x0000012c		ffe_coeff_set14_4	placeholder
0x00000130		ffe_coeff_set15_0	placeholder
0x00000134		ffe_coeff_set15_1	placeholder
0x00000138		ffe_coeff_set15_2	placeholder
0x0000013c		ffe_coeff_set15_3	placeholder
0x00000140		ffe_coeff_set15_4	placeholder
0x00000144	0x00000147	(Not allocated)
0x00000148		ffe_slice_level_set0	placeholder
0x0000014c		ffe_slice_level_set1	placeholder
0x00000150		ffe_slice_level_set2	placeholder
0x00000154		ffe_slice_level_set3	placeholder
0x00000158		ffe_slice_level_set4	placeholder
0x0000015c		ffe_slice_level_set5	placeholder
0x00000160		ffe_slice_level_set6	placeholder
0x00000164		ffe_slice_level_set7	placeholder
0x00000168		ffe_slice_level_set8	placeholder
0x0000016c		ffe_slice_level_set9	placeholder
0x00000170		ffe_slice_level_set10	placeholder
0x00000174		ffe_slice_level_set11	placeholder
0x00000178		ffe_slice_level_set12	placeholder
0x0000017c		ffe_slice_level_set13	placeholder
0x00000180		ffe_slice_level_set14	placeholder
0x00000184		ffe_slice_level_set15	placeholder
0x00000188		ffe_err_level_m1m3_set0	placeholder
0x0000018c		ffe_err_level_p1p3_set0	placeholder
0x00000190		ffe_err_level_m1m3_set1	placeholder
0x00000194		ffe_err_level_p1p3_set1	placeholder
0x00000198		ffe_err_level_m1m3_set2	placeholder
0x0000019c		ffe_err_level_p1p3_set2	placeholder
0x000001a0		ffe_err_level_m1m3_set3	placeholder
0x000001a4		ffe_err_level_p1p3_set3	placeholder
0x000001a8		ffe_err_level_m1m3_set4	placeholder
0x000001ac		ffe_err_level_p1p3_set4	placeholder
0x000001b0		ffe_err_level_m1m3_set5	placeholder
0x000001b4		ffe_err_level_p1p3_set5	placeholder
0x000001b8		ffe_err_level_m1m3_set6	placeholder
0x000001bc		ffe_err_level_p1p3_set6	placeholder
0x000001c0		ffe_err_level_m1m3_set7	placeholder
0x000001c4		ffe_err_level_p1p3_set7	placeholder
0x000001c8		ffe_err_level_m1m3_set8	placeholder
0x000001cc		ffe_err_level_p1p3_set8	placeholder
0x000001d0		ffe_err_level_m1m3_set9	placeholder
0x000001d4		ffe_err_level_p1p3_set9	placeholder
0x000001d8		ffe_err_level_m1m3_set10	placeholder
0x000001dc		ffe_err_level_p1p3_set10	placeholder
0x000001e0		ffe_err_level_m1m3_set11	placeholder
0x000001e4		ffe_err_level_p1p3_set11	placeholder
0x000001e8		ffe_err_level_m1m3_set12	placeholder
0x000001ec		ffe_err_level_p1p3_set12	placeholder
0x000001f0		ffe_err_level_m1m3_set13	placeholder
0x000001f4		ffe_err_level_p1p3_set13	placeholder
0x000001f8		ffe_err_level_m1m3_set14	placeholder
0x000001fc		ffe_err_level_p1p3_set14	placeholder
0x00000200		ffe_err_level_m1m3_set15	placeholder
0x00000204		ffe_err_level_p1p3_set15	placeholder
0x00000208		rx_dump_mem_ctrl	placeholder
0x0000020c		rx_dump_mem_apb_rd_data	placeholder
0x00000210		rx_dump_mem_apb_rd_en	placeholder
0x00000214		rx_dump_mem_apb_en	placeholder
0x00000218		rx_data_path_control_1	placeholder
0x0000021c		adp_msb_lsb_swap_ctrl	placeholder
0x00000220		ffe_float_tap_position1	placeholder
0x00000224		ffe_float_tap_position2	placeholder
0x00000228		ffe_float_tap_position3	placeholder
0x0000022c		rxeq_clock_gating_ctrl_0	placeholder
0x00000230		rxeq_clock_gating_ctrl_1	placeholder
0x00000234		rxeq_clock_gating_ctrl_2	placeholder
0x00000238		rxeq_clock_gating_ctrl_3	placeholder
0x0000023c		rxeq_clock_gating_ctrl_4	placeholder
0x00000240		rxeq_clock_gating_ctrl_6	placeholder
0x00000244		rxeq_clock_gating_ctrl_7	placeholder
0x00000248		rxeq_clock_gating_ctrl_8	placeholder
0x0000024c	0x0000028b	(Not allocated)
0x0000028c		adc_slicer_level_set0_control	placeholder
0x00000290		adc_slicer_level_set1_control	placeholder
0x00000294		adc_slicer_level_set2_control	placeholder
0x00000298		adc_slicer_level_set3_control	placeholder
0x0000029c		adc_slicer_level_set4_control	placeholder
0x000002a0		adc_slicer_level_set5_control	placeholder
0x000002a4		adc_slicer_level_set6_control	placeholder
0x000002a8		adc_slicer_level_set7_control	placeholder
0x000002ac		adc_slicer_level_set8_control	placeholder
0x000002b0		adc_slicer_level_set9_control	placeholder
0x000002b4		adc_slicer_level_set10_control	placeholder
0x000002b8		adc_slicer_level_set11_control	placeholder
0x000002bc		adc_slicer_level_set12_control	placeholder
0x000002c0		adc_slicer_level_set13_control	placeholder
0x000002c4		adc_slicer_level_set14_control	placeholder
0x000002c8		adc_slicer_level_set15_control	placeholder
0x000002cc		adc_err_level_set0_control	placeholder
0x000002d0		adc_err_level_set1_control	placeholder
0x000002d4		adc_err_level_set2_control	placeholder
0x000002d8		adc_err_level_set3_control	placeholder
0x000002dc		adc_err_level_set4_control	placeholder
0x000002e0		adc_err_level_set5_control	placeholder
0x000002e4		adc_err_level_set6_control	placeholder
0x000002e8		adc_err_level_set7_control	placeholder
0x000002ec		adc_err_level_set8_control	placeholder
0x000002f0		adc_err_level_set9_control	placeholder
0x000002f4		adc_err_level_set10_control	placeholder
0x000002f8		adc_err_level_set11_control	placeholder
0x000002fc		adc_err_level_set12_control	placeholder
0x00000300		adc_err_level_set13_control	placeholder
0x00000304		adc_err_level_set14_control	placeholder
0x00000308		adc_err_level_set15_control	placeholder
0x0000030c		rxsararray_valid_calassist_ctrl0	Rx SAR Array Valid Calibration Assistance Control
0x00000310		rxsararray_valid_calassist_ctrl1	Rx SAR Array Valid Calibration Assistance Control
0x00000314		rxsararray_valid_calassist_ctrl2	Rx SAR Array Valid Calibration Assistance Control
0x00000318		rxsararray_valid_calassist_status	Rx SAR Array Valid Calibration Assistance Status
0x0000031c		rxsar_calassist_ctrl	Rx SAR Calibration Assistance Control
0x00000320		rxsar_calassist_status	Rx SAR Calibration Assistance Status
0x00000324	0x000003eb	(Not allocated)
0x000003ec		main_fsm_control_6	placeholder
0x000003f0		main_fsm_control_0	placeholder
0x000003f4		main_fsm_status_0	placeholder
0x000003f8		main_fsm_control_1	placeholder
0x000003fc		main_fsm_control_2	placeholder
0x00000400		main_fsm_control_3	placeholder
0x00000404		taps_set_control	placeholder
0x00000408		rx_gearbox_ctrl	Rx Gearbox Control
0x0000040c		main_fsm_control_4	placeholder
0x00000410		main_fsm_control_5	placeholder
0x00000414		vref_control_1	placeholder
0x00000418		vref_control_2	placeholder
0x0000041c		vref_control_3	placeholder
0x00000420		vref_control_4	placeholder
0x00000424		vref_control_5	placeholder
0x00000428		vref_control_6	placeholder
0x0000042c	0x0000042f	(Not allocated)
0x00000430		vref_status_0	placeholder
0x00000434		vga_control_6	placeholder
0x00000438		vga_control_5	placeholder
0x0000043c		vga_control_4	placeholder
0x00000440		vga_control_0	placeholder
0x00000444		vga_control_1	placeholder
0x00000448		vga_control_2	placeholder
0x0000044c		vga_control_3	placeholder
0x00000450		vga_status_0	placeholder
0x00000454		jpp_control_1	placeholder
0x00000458		jpp_control_2	placeholder
0x0000045c	0x0000045f	(Not allocated)
0x00000460		ffe_control_0	placeholder
0x00000464		ffe_control_1	placeholder
0x00000468		ffe_control_2	placeholder
0x0000046c		ffe_control_3	placeholder
0x00000470		ffe_control_4	placeholder
0x00000474		ffe_control_5	placeholder
0x00000478	0x0000047b	(Not allocated)
0x0000047c		ffe_status_0	placeholder
0x00000480	0x0000048f	(Not allocated)
0x00000490		hist_control_0	placeholder
0x00000494		hist_control_1	placeholder
0x00000498		hist_control_2	placeholder
0x0000049c		hist_control_3	placeholder
0x000004a0		hist_control_4	placeholder
0x000004a4		hist_control_5	placeholder
0x000004a8		hist_control_6	placeholder
0x000004ac		hist_control_7	placeholder
0x000004b0		hist_control_8	placeholder
0x000004b4		hist_control_9	placeholder
0x000004b8		hist_control_10	placeholder
0x000004bc		hist_control_11	placeholder
0x000004c0		hist_control_12	placeholder
0x000004c4		hist_control_13	placeholder
0x000004c8		hist_status_0	placeholder
0x000004cc		hist_status_1	placeholder
0x000004d0		hist_status_2	placeholder
0x000004d4		hist_status_3	placeholder
0x000004d8		hist_status_4	placeholder
0x000004dc	0x000004df	(Not allocated)
0x000004e0		hist_status_5	placeholder
0x000004e4		hist_status_6	placeholder
0x000004e8		hist_status_7	placeholder
0x000004ec		hist_status_8	placeholder
0x000004f0		hist_status_9	placeholder
0x000004f4		hist_status_10	placeholder
0x000004f8		hist_status_11	placeholder
0x000004fc		hist_status_12	placeholder
0x00000500		hist_status_13	placeholder
0x00000504	0x0000050f	(Not allocated)
0x00000510		hist_status_14	placeholder
0x00000514		hist_status_15	placeholder
0x00000518		ops_control_1	placeholder
0x0000051c		ops_control_2	placeholder
0x00000520		ops_control_3	placeholder
0x00000524		ops_control_4	placeholder
0x00000528	0x0000052b	(Not allocated)
0x0000052c		ops_status_1	placeholder
0x00000530	0x00000533	(Not allocated)
0x00000534		ops_status_2	placeholder
0x00000538		adcvref_control_1	placeholder
0x0000053c		adcvref_control_2	placeholder
0x00000540		adcvref_control_3	placeholder
0x00000544		adcvref_control_4	placeholder
0x00000548		adcvref_control_5	placeholder
0x0000054c		adcvref_control_6	placeholder
0x00000550		adcvref_status_0	placeholder
0x00000554	0x0000055f	(Not allocated)
0x00000560		affe_control_0	placeholder
0x00000564		affe_control_1	placeholder
0x00000568		affe_control_2	placeholder
0x0000056c		affe_control_3	placeholder
0x00000570		affe_status_0	placeholder
0x00000574	0x0000057b	(Not allocated)
0x0000057c		ofc_control_0	placeholder
0x00000580		ofc_control_1a	placeholder
0x00000584		ofc_control_1b	placeholder
0x00000588		ofc_control_2	placeholder
0x0000058c		ofc_control_3	placeholder
0x00000590		ofc_status_0	placeholder
0x00000594		ffe_coeff_set0_frac_0	placeholder
0x00000598		ffe_coeff_set0_frac_1	placeholder
0x0000059c		ffe_coeff_set0_frac_2	placeholder
0x000005a0		ffe_coeff_set0_frac_3	placeholder
0x000005a4		ffe_coeff_set0_frac_4	placeholder
0x000005a8		ffe_coeff_set0_frac_5	placeholder
0x000005ac		ffe_coeff_set1_frac_0	placeholder
0x000005b0		ffe_coeff_set1_frac_1	placeholder
0x000005b4		ffe_coeff_set1_frac_2	placeholder
0x000005b8		ffe_coeff_set1_frac_3	placeholder
0x000005bc		ffe_coeff_set1_frac_4	placeholder
0x000005c0		ffe_coeff_set1_frac_5	placeholder
0x000005c4		ffe_coeff_set2_frac_0	placeholder
0x000005c8		ffe_coeff_set2_frac_1	placeholder
0x000005cc		ffe_coeff_set2_frac_2	placeholder
0x000005d0		ffe_coeff_set2_frac_3	placeholder
0x000005d4		ffe_coeff_set2_frac_4	placeholder
0x000005d8		ffe_coeff_set2_frac_5	placeholder
0x000005dc		ffe_coeff_set3_frac_0	placeholder
0x000005e0		ffe_coeff_set3_frac_1	placeholder
0x000005e4		ffe_coeff_set3_frac_2	placeholder
0x000005e8		ffe_coeff_set3_frac_3	placeholder
0x000005ec		ffe_coeff_set3_frac_4	placeholder
0x000005f0		ffe_coeff_set3_frac_5	placeholder
0x000005f4		ffe_coeff_set4_frac_0	placeholder
0x000005f8		ffe_coeff_set4_frac_1	placeholder
0x000005fc		ffe_coeff_set4_frac_2	placeholder
0x00000600		ffe_coeff_set4_frac_3	placeholder
0x00000604		ffe_coeff_set4_frac_4	placeholder
0x00000608		ffe_coeff_set4_frac_5	placeholder
0x0000060c		ffe_coeff_set5_frac_0	placeholder
0x00000610		ffe_coeff_set5_frac_1	placeholder
0x00000614		ffe_coeff_set5_frac_2	placeholder
0x00000618		ffe_coeff_set5_frac_3	placeholder
0x0000061c		ffe_coeff_set5_frac_4	placeholder
0x00000620		ffe_coeff_set5_frac_5	placeholder
0x00000624		ffe_coeff_set6_frac_0	placeholder
0x00000628		ffe_coeff_set6_frac_1	placeholder
0x0000062c		ffe_coeff_set6_frac_2	placeholder
0x00000630		ffe_coeff_set6_frac_3	placeholder
0x00000634		ffe_coeff_set6_frac_4	placeholder
0x00000638		ffe_coeff_set6_frac_5	placeholder
0x0000063c		ffe_coeff_set7_frac_0	placeholder
0x00000640		ffe_coeff_set7_frac_1	placeholder
0x00000644		ffe_coeff_set7_frac_2	placeholder
0x00000648		ffe_coeff_set7_frac_3	placeholder
0x0000064c		ffe_coeff_set7_frac_4	placeholder
0x00000650		ffe_coeff_set7_frac_5	placeholder
0x00000654		ffe_coeff_set8_frac_0	placeholder
0x00000658		ffe_coeff_set8_frac_1	placeholder
0x0000065c		ffe_coeff_set8_frac_2	placeholder
0x00000660		ffe_coeff_set8_frac_3	placeholder
0x00000664		ffe_coeff_set8_frac_4	placeholder
0x00000668		ffe_coeff_set8_frac_5	placeholder
0x0000066c		ffe_coeff_set9_frac_0	placeholder
0x00000670		ffe_coeff_set9_frac_1	placeholder
0x00000674		ffe_coeff_set9_frac_2	placeholder
0x00000678		ffe_coeff_set9_frac_3	placeholder
0x0000067c		ffe_coeff_set9_frac_4	placeholder
0x00000680		ffe_coeff_set9_frac_5	placeholder
0x00000684		ffe_coeff_set10_frac_0	placeholder
0x00000688		ffe_coeff_set10_frac_1	placeholder
0x0000068c		ffe_coeff_set10_frac_2	placeholder
0x00000690		ffe_coeff_set10_frac_3	placeholder
0x00000694		ffe_coeff_set10_frac_4	placeholder
0x00000698		ffe_coeff_set10_frac_5	placeholder
0x0000069c		ffe_coeff_set11_frac_0	placeholder
0x000006a0		ffe_coeff_set11_frac_1	placeholder
0x000006a4		ffe_coeff_set11_frac_2	placeholder
0x000006a8		ffe_coeff_set11_frac_3	placeholder
0x000006ac		ffe_coeff_set11_frac_4	placeholder
0x000006b0		ffe_coeff_set11_frac_5	placeholder
0x000006b4		ffe_coeff_set12_frac_0	placeholder
0x000006b8		ffe_coeff_set12_frac_1	placeholder
0x000006bc		ffe_coeff_set12_frac_2	placeholder
0x000006c0		ffe_coeff_set12_frac_3	placeholder
0x000006c4		ffe_coeff_set12_frac_4	placeholder
0x000006c8		ffe_coeff_set12_frac_5	placeholder
0x000006cc		ffe_coeff_set13_frac_0	placeholder
0x000006d0		ffe_coeff_set13_frac_1	placeholder
0x000006d4		ffe_coeff_set13_frac_2	placeholder
0x000006d8		ffe_coeff_set13_frac_3	placeholder
0x000006dc		ffe_coeff_set13_frac_4	placeholder
0x000006e0		ffe_coeff_set13_frac_5	placeholder
0x000006e4		ffe_coeff_set14_frac_0	placeholder
0x000006e8		ffe_coeff_set14_frac_1	placeholder
0x000006ec		ffe_coeff_set14_frac_2	placeholder
0x000006f0		ffe_coeff_set14_frac_3	placeholder
0x000006f4		ffe_coeff_set14_frac_4	placeholder
0x000006f8		ffe_coeff_set14_frac_5	placeholder
0x000006fc		ffe_coeff_set15_frac_0	placeholder
0x00000700		ffe_coeff_set15_frac_1	placeholder
0x00000704		ffe_coeff_set15_frac_2	placeholder
0x00000708		ffe_coeff_set15_frac_3	placeholder
0x0000070c		ffe_coeff_set15_frac_4	placeholder
0x00000710		ffe_coeff_set15_frac_5	placeholder
0x00000714		ffe_err_level_frac_set0_0	placeholder
0x00000718		ffe_err_level_frac_set1_0	placeholder
0x0000071c		ffe_err_level_frac_set2_0	placeholder
0x00000720		ffe_err_level_frac_set3_0	placeholder
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0x000008ec		cdr_ffe_pre1_set4to7	Rx SAR Array valid
0x000008f0		cdr_ffe_pre1_set8to11	Rx SAR Array valid
0x000008f4		cdr_ffe_pre1_set12to15	Rx SAR Array valid
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0x000008fc		cdr_ffe_slicer_level_set1_control	placeholder
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0x0000090c		cdr_ffe_slicer_level_set4_control	placeholder
0x00000910		cdr_ffe_slicer_level_set5_control	placeholder
0x00000914		cdr_ffe_slicer_level_set6_control	placeholder
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0x0000093c	0x0000093f	(Not allocated)
0x00000940		cdr_ffe_err_level_m1m3_set0	placeholder
0x00000944		cdr_ffe_err_level_p1p3_set0	placeholder
0x00000948		cdr_ffe_err_level_m1m3_set1	placeholder
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0x00000984		cdr_ffe_err_level_p1p3_set8	placeholder
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0x0000098c		cdr_ffe_err_level_p1p3_set9	placeholder
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0x000009c4	0x000009c7	(Not allocated)
0x000009c8		cdr_ffe_post1_set0to3	Rx SAR Array valid
0x000009cc		cdr_ffe_post1_set4to7	Rx SAR Array valid
0x000009d0		cdr_ffe_post1_set8to11	Rx SAR Array valid
0x000009d4		cdr_ffe_post1_set12to15	Rx SAR Array valid
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0x000009dc		cdr_ffe_control_1	placeholder
0x000009e0		cdr_ffe_control_2	placeholder
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0x000009ec		cdr_ffe_vref_control_2	placeholder
0x000009f0		cdr_ffe_vref_control_3	placeholder
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0x000009f8		cdr_ffe_vref_control_5	placeholder
0x000009fc		cdr_ffe_vref_control_6	placeholder
0x00000a00	0x00000a03	(Not allocated)
0x00000a04		cdr_ffe_ofc_control_0	placeholder
0x00000a08		cdr_ffe_ofc_control_1a	placeholder
0x00000a0c		cdr_ffe_ofc_control_1b	placeholder
0x00000a10		cdr_ffe_ofc_control_2	placeholder
0x00000a14		cdr_ffe_ofc_control_3	placeholder
0x00000a18		cdr_ffe_ofc_status_0	placeholder
0x00000a1c		cdr_ffe_pre1_set0to3_frac	Rx SAR Array valid
0x00000a20		cdr_ffe_pre1_set4to7_frac	Rx SAR Array valid
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0x00000a28		cdr_ffe_pre1_set12to15_frac	Rx SAR Array valid
0x00000a2c		cdr_ffe_post1_set0to3_frac	Rx SAR Array valid
0x00000a30		cdr_ffe_post1_set4to7_frac	Rx SAR Array valid
0x00000a34		cdr_ffe_post1_set8to11_frac	Rx SAR Array valid
0x00000a38		cdr_ffe_post1_set12to15_frac	Rx SAR Array valid
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0x00000a40		cdr_ffe_err_level_frac_set1_0	placeholder
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0x00000a54		cdr_ffe_err_level_frac_set6_0	placeholder
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0x00000a5c		cdr_ffe_err_level_frac_set8_0	placeholder
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0x00000a7c		cdr_ffe_control_3	placeholder
0x00000a80		cdr_ffe_pre3_set0to3	Rx SAR Array valid
0x00000a84		cdr_ffe_pre3_set4to7	Rx SAR Array valid
0x00000a88		cdr_ffe_pre3_set8to11	Rx SAR Array valid
0x00000a8c		cdr_ffe_pre3_set12to15	Rx SAR Array valid
0x00000a90		cdr_ffe_pre2_set0to3	Rx SAR Array valid
0x00000a94		cdr_ffe_pre2_set4to7	Rx SAR Array valid
0x00000a98		cdr_ffe_pre2_set8to11	Rx SAR Array valid
0x00000a9c		cdr_ffe_pre2_set12to15	Rx SAR Array valid
0x00000aa0		cdr_ffe_post2_set0to3	Rx SAR Array valid
0x00000aa4		cdr_ffe_post2_set4to7	Rx SAR Array valid
0x00000aa8		cdr_ffe_post2_set8to11	Rx SAR Array valid
0x00000aac		cdr_ffe_post2_set12to15	Rx SAR Array valid
0x00000ab0		cdr_ffe_post3_set0to3	Rx SAR Array valid
0x00000ab4		cdr_ffe_post3_set4to7	Rx SAR Array valid
0x00000ab8		cdr_ffe_post3_set8to11	Rx SAR Array valid
0x00000abc		cdr_ffe_post3_set12to15	Rx SAR Array valid
0x00000ac0		cdr_ffe_post4_set0to3	Rx SAR Array valid
0x00000ac4		cdr_ffe_post4_set4to7	Rx SAR Array valid
0x00000ac8		cdr_ffe_post4_set8to11	Rx SAR Array valid
0x00000acc		cdr_ffe_post4_set12to15	Rx SAR Array valid
0x00000ad0		cdr_ffe_pre3_set0to3_frac	Rx SAR Array valid
0x00000ad4		cdr_ffe_pre3_set4to7_frac	Rx SAR Array valid
0x00000ad8		cdr_ffe_pre3_set8to11_frac	Rx SAR Array valid
0x00000adc		cdr_ffe_pre3_set12to15_frac	Rx SAR Array valid
0x00000ae0		cdr_ffe_pre2_set0to3_frac	Rx SAR Array valid
0x00000ae4		cdr_ffe_pre2_set4to7_frac	Rx SAR Array valid
0x00000ae8		cdr_ffe_pre2_set8to11_frac	Rx SAR Array valid
0x00000aec		cdr_ffe_pre2_set12to15_frac	Rx SAR Array valid
0x00000af0		cdr_ffe_post2_set0to3_frac	Rx SAR Array valid
0x00000af4		cdr_ffe_post2_set4to7_frac	Rx SAR Array valid
0x00000af8		cdr_ffe_post2_set8to11_frac	Rx SAR Array valid
0x00000afc		cdr_ffe_post2_set12to15_frac	Rx SAR Array valid
0x00000b00		cdr_ffe_post3_set0to3_frac	Rx SAR Array valid
0x00000b04		cdr_ffe_post3_set4to7_frac	Rx SAR Array valid
0x00000b08		cdr_ffe_post3_set8to11_frac	Rx SAR Array valid
0x00000b0c		cdr_ffe_post3_set12to15_frac	Rx SAR Array valid
0x00000b10		cdr_ffe_post4_set0to3_frac	Rx SAR Array valid
0x00000b14		cdr_ffe_post4_set4to7_frac	Rx SAR Array valid
0x00000b18		cdr_ffe_post4_set8to11_frac	Rx SAR Array valid
0x00000b1c		cdr_ffe_post4_set12to15_frac	Rx SAR Array valid
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0x00000b24		affe_if_control_0	placeholder
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0x00000b68		ops_taps_b1_sar_0to3	placeholder
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0x00000b70		ops_taps_b1_sar_8to11	placeholder
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0x00000b88		ops_taps_b1_sar_32to35	placeholder
0x00000b8c		ops_taps_b1_sar_36to39	placeholder
0x00000b90		ops_taps_b1_sar_40to43	placeholder
0x00000b94		ops_taps_b1_sar_44to47	placeholder
0x00000b98		ops_taps_b1_sar_48to51	placeholder
0x00000b9c		ops_taps_b1_sar_52to55	placeholder
0x00000ba0		ops_taps_b1_sar_56to59	placeholder
0x00000ba4		ops_taps_b1_sar_60to63	placeholder
0x00000ba8		ops_taps_b2_sar_0to3	placeholder
0x00000bac		ops_taps_b2_sar_4to7	placeholder
0x00000bb0		ops_taps_b2_sar_8to11	placeholder
0x00000bb4		ops_taps_b2_sar_12to15	placeholder
0x00000bb8		ops_taps_b2_sar_16to19	placeholder
0x00000bbc		ops_taps_b2_sar_20to23	placeholder
0x00000bc0		ops_taps_b2_sar_24to27	placeholder
0x00000bc4		ops_taps_b2_sar_28to31	placeholder
0x00000bc8		ops_taps_b2_sar_32to35	placeholder
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0x00000bd4		ops_taps_b2_sar_44to47	placeholder
0x00000bd8		ops_taps_b2_sar_48to51	placeholder
0x00000bdc		ops_taps_b2_sar_52to55	placeholder
0x00000be0		ops_taps_b2_sar_56to59	placeholder
0x00000be4		ops_taps_b2_sar_60to63	placeholder
0x00000be8		ops_taps_b3_sar_0to3	placeholder
0x00000bec		ops_taps_b3_sar_4to7	placeholder
0x00000bf0		ops_taps_b3_sar_8to11	placeholder
0x00000bf4		ops_taps_b3_sar_12to15	placeholder
0x00000bf8		ops_taps_b3_sar_16to19	placeholder
0x00000bfc		ops_taps_b3_sar_20to23	placeholder
0x00000c00		ops_taps_b3_sar_24to27	placeholder
0x00000c04		ops_taps_b3_sar_28to31	placeholder
0x00000c08		ops_taps_b3_sar_32to35	placeholder
0x00000c0c		ops_taps_b3_sar_36to39	placeholder
0x00000c10		ops_taps_b3_sar_40to43	placeholder
0x00000c14		ops_taps_b3_sar_44to47	placeholder
0x00000c18		ops_taps_b3_sar_48to51	placeholder
0x00000c1c		ops_taps_b3_sar_52to55	placeholder
0x00000c20		ops_taps_b3_sar_56to59	placeholder
0x00000c24		ops_taps_b3_sar_60to63	placeholder
0x00000c28		ops_taps_b4_sar_0to3	placeholder
0x00000c2c		ops_taps_b4_sar_4to7	placeholder
0x00000c30		ops_taps_b4_sar_8to11	placeholder
0x00000c34		ops_taps_b4_sar_12to15	placeholder
0x00000c38		ops_taps_b4_sar_16to19	placeholder
0x00000c3c		ops_taps_b4_sar_20to23	placeholder
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0x00000c44		ops_taps_b4_sar_28to31	placeholder
0x00000c48		ops_taps_b4_sar_32to35	placeholder
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0x00000c54		ops_taps_b4_sar_44to47	placeholder
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0x00000c5c		ops_taps_b4_sar_52to55	placeholder
0x00000c60		ops_taps_b4_sar_56to59	placeholder
0x00000c64		ops_taps_b4_sar_60to63	placeholder
0x00000c68		ops_taps_b5_sar_0to3	placeholder
0x00000c6c		ops_taps_b5_sar_4to7	placeholder
0x00000c70		ops_taps_b5_sar_8to11	placeholder
0x00000c74		ops_taps_b5_sar_12to15	placeholder
0x00000c78		ops_taps_b5_sar_16to19	placeholder
0x00000c7c		ops_taps_b5_sar_20to23	placeholder
0x00000c80		ops_taps_b5_sar_24to27	placeholder
0x00000c84		ops_taps_b5_sar_28to31	placeholder
0x00000c88		ops_taps_b5_sar_32to35	placeholder
0x00000c8c		ops_taps_b5_sar_36to39	placeholder
0x00000c90		ops_taps_b5_sar_40to43	placeholder
0x00000c94		ops_taps_b5_sar_44to47	placeholder
0x00000c98		ops_taps_b5_sar_48to51	placeholder
0x00000c9c		ops_taps_b5_sar_52to55	placeholder
0x00000ca0		ops_taps_b5_sar_56to59	placeholder
0x00000ca4		ops_taps_b5_sar_60to63	placeholder
0x00000ca8		ops_taps_fra_b0_sar_0to3	placeholder
0x00000cac		ops_taps_fra_b0_sar_4to7	placeholder
0x00000cb0		ops_taps_fra_b0_sar_8to11	placeholder
0x00000cb4		ops_taps_fra_b0_sar_12to15	placeholder
0x00000cb8		ops_taps_fra_b0_sar_16to19	placeholder
0x00000cbc		ops_taps_fra_b0_sar_20to23	placeholder
0x00000cc0		ops_taps_fra_b0_sar_24to27	placeholder
0x00000cc4		ops_taps_fra_b0_sar_28to31	placeholder
0x00000cc8		ops_taps_fra_b0_sar_32to35	placeholder
0x00000ccc		ops_taps_fra_b0_sar_36to39	placeholder
0x00000cd0		ops_taps_fra_b0_sar_40to43	placeholder
0x00000cd4		ops_taps_fra_b0_sar_44to47	placeholder
0x00000cd8		ops_taps_fra_b0_sar_48to51	placeholder
0x00000cdc		ops_taps_fra_b0_sar_52to55	placeholder
0x00000ce0		ops_taps_fra_b0_sar_56to59	placeholder
0x00000ce4		ops_taps_fra_b0_sar_60to63	placeholder
0x00000ce8		ops_taps_fra_b1_sar_0to3	placeholder
0x00000cec		ops_taps_fra_b1_sar_4to7	placeholder
0x00000cf0		ops_taps_fra_b1_sar_8to11	placeholder
0x00000cf4		ops_taps_fra_b1_sar_12to15	placeholder
0x00000cf8		ops_taps_fra_b1_sar_16to19	placeholder
0x00000cfc		ops_taps_fra_b1_sar_20to23	placeholder
0x00000d00		ops_taps_fra_b1_sar_24to27	placeholder
0x00000d04		ops_taps_fra_b1_sar_28to31	placeholder
0x00000d08		ops_taps_fra_b1_sar_32to35	placeholder
0x00000d0c		ops_taps_fra_b1_sar_36to39	placeholder
0x00000d10		ops_taps_fra_b1_sar_40to43	placeholder
0x00000d14		ops_taps_fra_b1_sar_44to47	placeholder
0x00000d18		ops_taps_fra_b1_sar_48to51	placeholder
0x00000d1c		ops_taps_fra_b1_sar_52to55	placeholder
0x00000d20		ops_taps_fra_b1_sar_56to59	placeholder
0x00000d24		ops_taps_fra_b1_sar_60to63	placeholder
0x00000d28		ops_taps_fra_b2_sar_0to3	placeholder
0x00000d2c		ops_taps_fra_b2_sar_4to7	placeholder
0x00000d30		ops_taps_fra_b2_sar_8to11	placeholder
0x00000d34		ops_taps_fra_b2_sar_12to15	placeholder
0x00000d38		ops_taps_fra_b2_sar_16to19	placeholder
0x00000d3c		ops_taps_fra_b2_sar_20to23	placeholder
0x00000d40		ops_taps_fra_b2_sar_24to27	placeholder
0x00000d44		ops_taps_fra_b2_sar_28to31	placeholder
0x00000d48		ops_taps_fra_b2_sar_32to35	placeholder
0x00000d4c		ops_taps_fra_b2_sar_36to39	placeholder
0x00000d50		ops_taps_fra_b2_sar_40to43	placeholder
0x00000d54		ops_taps_fra_b2_sar_44to47	placeholder
0x00000d58		ops_taps_fra_b2_sar_48to51	placeholder
0x00000d5c		ops_taps_fra_b2_sar_52to55	placeholder
0x00000d60		ops_taps_fra_b2_sar_56to59	placeholder
0x00000d64		ops_taps_fra_b2_sar_60to63	placeholder
0x00000d68		ops_taps_fra_b3_sar_0to3	placeholder
0x00000d6c		ops_taps_fra_b3_sar_4to7	placeholder
0x00000d70		ops_taps_fra_b3_sar_8to11	placeholder
0x00000d74		ops_taps_fra_b3_sar_12to15	placeholder
0x00000d78		ops_taps_fra_b3_sar_16to19	placeholder
0x00000d7c		ops_taps_fra_b3_sar_20to23	placeholder
0x00000d80		ops_taps_fra_b3_sar_24to27	placeholder
0x00000d84		ops_taps_fra_b3_sar_28to31	placeholder
0x00000d88		ops_taps_fra_b3_sar_32to35	placeholder
0x00000d8c		ops_taps_fra_b3_sar_36to39	placeholder
0x00000d90		ops_taps_fra_b3_sar_40to43	placeholder
0x00000d94		ops_taps_fra_b3_sar_44to47	placeholder
0x00000d98		ops_taps_fra_b3_sar_48to51	placeholder
0x00000d9c		ops_taps_fra_b3_sar_52to55	placeholder
0x00000da0		ops_taps_fra_b3_sar_56to59	placeholder
0x00000da4		ops_taps_fra_b3_sar_60to63	placeholder
0x00000da8		ops_taps_fra_b4_sar_0to3	placeholder
0x00000dac		ops_taps_fra_b4_sar_4to7	placeholder
0x00000db0		ops_taps_fra_b4_sar_8to11	placeholder
0x00000db4		ops_taps_fra_b4_sar_12to15	placeholder
0x00000db8		ops_taps_fra_b4_sar_16to19	placeholder
0x00000dbc		ops_taps_fra_b4_sar_20to23	placeholder
0x00000dc0		ops_taps_fra_b4_sar_24to27	placeholder
0x00000dc4		ops_taps_fra_b4_sar_28to31	placeholder
0x00000dc8		ops_taps_fra_b4_sar_32to35	placeholder
0x00000dcc		ops_taps_fra_b4_sar_36to39	placeholder
0x00000dd0		ops_taps_fra_b4_sar_40to43	placeholder
0x00000dd4		ops_taps_fra_b4_sar_44to47	placeholder
0x00000dd8		ops_taps_fra_b4_sar_48to51	placeholder
0x00000ddc		ops_taps_fra_b4_sar_52to55	placeholder
0x00000de0		ops_taps_fra_b4_sar_56to59	placeholder
0x00000de4		ops_taps_fra_b4_sar_60to63	placeholder
0x00000de8		ops_taps_fra_b5_sar_0to3	placeholder
0x00000dec		ops_taps_fra_b5_sar_4to7	placeholder
0x00000df0		ops_taps_fra_b5_sar_8to11	placeholder
0x00000df4		ops_taps_fra_b5_sar_12to15	placeholder
0x00000df8		ops_taps_fra_b5_sar_16to19	placeholder
0x00000dfc		ops_taps_fra_b5_sar_20to23	placeholder
0x00000e00		ops_taps_fra_b5_sar_24to27	placeholder
0x00000e04		ops_taps_fra_b5_sar_28to31	placeholder
0x00000e08		ops_taps_fra_b5_sar_32to35	placeholder
0x00000e0c		ops_taps_fra_b5_sar_36to39	placeholder
0x00000e10		ops_taps_fra_b5_sar_40to43	placeholder
0x00000e14		ops_taps_fra_b5_sar_44to47	placeholder
0x00000e18		ops_taps_fra_b5_sar_48to51	placeholder
0x00000e1c		ops_taps_fra_b5_sar_52to55	placeholder
0x00000e20		ops_taps_fra_b5_sar_56to59	placeholder
0x00000e24		ops_taps_fra_b5_sar_60to63	placeholder
0x00000e28		ofc_control_4	placeholder
0x00000e2c		ofc_control_5	placeholder
0x00000e30		ofc_control_6	placeholder
0x00000e34		ofc_control_7	placeholder
0x00000e38		cdr_ffe_ofc_control_4	placeholder
0x00000e3c		cdr_ffe_ofc_control_5	placeholder
0x00000e40		cdr_ffe_ofc_control_6	placeholder
0x00000e44		cdr_ffe_ofc_control_7	placeholder
0x00000e48		adcofc_control_4	placeholder
0x00000e4c		adcofc_control_5	placeholder
0x00000e50		adcofc_control_6	placeholder
0x00000e54		adcofc_control_7	placeholder
0x00000e58	0x00000ef7	(Not allocated)
0x00000ef8		rx_sigdet_venv_ctrl1	placeholder
0x00000efc		rx_sigdet_venv_ctrl2	placeholder
0x00000f00		rx_sigdet_venv_ctrl3	placeholder
0x00000f04		rx_sigdet_venv_status	placeholder
0x00000f08		rx_sigdet_venv_status_clr	placeholder
0x00000f0c	0x00000fd7	(Not allocated)
0x00000fd8		rxword_rw_spare_0	Spare RW register
0x00000fdc		rxword_rw_spare_1	Spare RW register
0x00000fe0		rxword_rw_spare_2	Spare RW register
0x00000fe4		rxword_rw_spare_3	Spare RW register
0x00000fe8		rxword_ro_spare_0	Spare RO register
0x00000fec		rxword_ro_spare_1	Spare RO register

Register Details for AddressMap abc_soc_top/dlnk/jesdabc3/pipe_phy_1x4lane_map/pipe_phy_VERSA/versa_PMA0/PMA_RXWORD_Q3/PMA_RXWORD_regs

Note: AddressOffsets before register name are offsets inside AddressMap (that is what the "+" means)

+0x00000000 Register(32 bit) ffe_coeff_set0_0
placeholder
placeholder

Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x07836000 at NOC.jesd__axi (Mem)

Access RW/V

Reset Information
Prio	Type	Properties	Value/Mask (hex)
0	PowerUp		0x00000000
		Unaffected	0x0000c0c0
		Undefined	0x0000c0c0

Bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Reset	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	-	-	0	0	0	0	0	0	-	-	0	0	0	0	0	0
Name	ffe_coeff_set0_coeff_post1								ffe_coeff_set0_coeff_pre1								-		ffe_coeff_set0_coeff_pre2						-		ffe_coeff_set0_coeff_pre3
Access	RW/V								RW/V								-		RW/V						-		RW/V

[31:24] RW/V	ffe_coeff_set0_coeff_post1 ffe_coeff_set0_coeff_post1[31:24] set0 ffe post cursor 1 coeff Reset: hex:0x00;
[23:16] RW/V	ffe_coeff_set0_coeff_pre1 ffe_coeff_set0_coeff_pre1[23:16] set0 ffe pre cursor 1 coeff Reset: hex:0x00;
[13:08] RW/V	ffe_coeff_set0_coeff_pre2 ffe_coeff_set0_coeff_pre2[13:8] set0 ffe pre cursor 2 coeff Reset: hex:0x00;
[05:00] RW/V	ffe_coeff_set0_coeff_pre3 ffe_coeff_set0_coeff_pre3[5:0] set0 ffe pre cursor 3 coeff Reset: hex:0x00;

Bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Reset	-	-	0	0	0	0	0	0	-	-	0	0	0	0	0	0	-	-	0	0	0	0	0	0	0	0	0	0	0	0	0	0
Name	-		ffe_coeff_set0_coeff_post5						-		ffe_coeff_set0_coeff_post4						-		ffe_coeff_set0_coeff_post3						ffe_coeff_set0_coeff_post2
Access	-		RW/V						-		RW/V						-		RW/V						RW/V

[29:24] RW/V	ffe_coeff_set0_coeff_post5 ffe_coeff_set0_coeff_post5[29:24] set0 ffe post cursor 5 coeff Reset: hex:0x00;
[21:16] RW/V	ffe_coeff_set0_coeff_post4 ffe_coeff_set0_coeff_post4[21:16] set0 ffe post cursor 4 coeff Reset: hex:0x00;
[13:08] RW/V	ffe_coeff_set0_coeff_post3 ffe_coeff_set0_coeff_post3[13:8] set0 ffe post cursor 3 coeff Reset: hex:0x00;
[07:00] RW/V	ffe_coeff_set0_coeff_post2 ffe_coeff_set0_coeff_post2[7:0] set0 ffe post cursor 2 coeff Reset: hex:0x00;

Bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Reset	0	0	0	0	0	0	0	0	-	-	0	0	0	0	0	0	-	-	0	0	0	0	0	0	-	-	0	0	0	0	0	0
Name	ffe_coeff_set0_coeff_post10				ffe_coeff_set0_coeff_post9				-		ffe_coeff_set0_coeff_post8						-		ffe_coeff_set0_coeff_post7						-		ffe_coeff_set0_coeff_post6
Access	RW/V				RW/V				-		RW/V						-		RW/V						-		RW/V

[31:28] RW/V	ffe_coeff_set0_coeff_post10 ffe_coeff_set0_coeff_post10[31:28] set0 ffe post cursor 10 coeff Reset: hex:0x0;
[27:24] RW/V	ffe_coeff_set0_coeff_post9 ffe_coeff_set0_coeff_post9[27:24] set0 ffe post cursor 9 coeff Reset: hex:0x0;
[21:16] RW/V	ffe_coeff_set0_coeff_post8 ffe_coeff_set0_coeff_post8[21:16] set0 ffe post cursor 8 coeff Reset: hex:0x00;
[13:08] RW/V	ffe_coeff_set0_coeff_post7 ffe_coeff_set0_coeff_post7[13:8] set0 ffe post cursor 7 coeff Reset: hex:0x00;
[05:00] RW/V	ffe_coeff_set0_coeff_post6 ffe_coeff_set0_coeff_post6[5:0] set0 ffe post cursor 6 coeff Reset: hex:0x00;

Bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Reset	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
Name	ffe_coeff_set0_bankB_float3				ffe_coeff_set0_bankB_float2				ffe_coeff_set0_bankB_float1				ffe_coeff_set0_bankA_float3				ffe_coeff_set0_bankA_float2				ffe_coeff_set0_bankA_float1				ffe_coeff_set0_coeff_post12				ffe_coeff_set0_coeff_post11
Access	RW/V				RW/V				RW/V				RW/V				RW/V				RW/V				RW/V				RW/V

[31:28] RW/V	ffe_coeff_set0_bankB_float3 ffe_coeff_set0_bankB_float3[31:28] set0 ffe bankB floating 3 coeff Reset: hex:0x0;
[27:24] RW/V	ffe_coeff_set0_bankB_float2 ffe_coeff_set0_bankB_float2[27:24] set0 ffe bankB floating 2 coeff Reset: hex:0x0;
[23:20] RW/V	ffe_coeff_set0_bankB_float1 ffe_coeff_set0_bankB_float1[23:20] set0 ffe bankB floating 1 coeff Reset: hex:0x0;
[19:16] RW/V	ffe_coeff_set0_bankA_float3 ffe_coeff_set0_bankA_float3[19:16] set0 ffe bankA floating 3 coeff Reset: hex:0x0;
[15:12] RW/V	ffe_coeff_set0_bankA_float2 ffe_coeff_set0_bankA_float2[15:12] set0 ffe bankA floating 2 coeff Reset: hex:0x0;
[11:08] RW/V	ffe_coeff_set0_bankA_float1 ffe_coeff_set0_bankA_float1[11:8] set0 ffe bankA floating 1 coeff Reset: hex:0x0;
[07:04] RW/V	ffe_coeff_set0_coeff_post12 ffe_coeff_set0_coeff_post12[7:4] set0 ffe post cursor 12 coeff Reset: hex:0x0;
[03:00] RW/V	ffe_coeff_set0_coeff_post11 ffe_coeff_set0_coeff_post11[3:0] set0 ffe post cursor 11 coeff Reset: hex:0x0;

Bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Reset	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	0	0	0	0	0	0	0	0	0	0
Name	-																				ffe_coeff_set0_bankC_float3				ffe_coeff_set0_bankC_float2				ffe_coeff_set0_bankC_float1
Access	-																				RW/V				RW/V				RW/V

Bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Reset	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	-	-	0	0	0	0	0	0	-	-	0	0	0	0	0	0
Name	ffe_coeff_set1_coeff_post1								ffe_coeff_set1_coeff_pre1								-		ffe_coeff_set1_coeff_pre2						-		ffe_coeff_set1_coeff_pre3
Access	RW/V								RW/V								-		RW/V						-		RW/V

[31:24] RW/V	ffe_coeff_set1_coeff_post1 ffe_coeff_set1_coeff_post1[31:24] set1 ffe post cursor 1 coeff Reset: hex:0x00;
[23:16] RW/V	ffe_coeff_set1_coeff_pre1 ffe_coeff_set1_coeff_pre1[23:16] set1 ffe pre cursor 1 coeff Reset: hex:0x00;
[13:08] RW/V	ffe_coeff_set1_coeff_pre2 ffe_coeff_set1_coeff_pre2[13:8] set1 ffe pre cursor 2 coeff Reset: hex:0x00;
[05:00] RW/V	ffe_coeff_set1_coeff_pre3 ffe_coeff_set1_coeff_pre3[5:0] set1 ffe pre cursor 3 coeff Reset: hex:0x00;

Bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Reset	-	-	0	0	0	0	0	0	-	-	0	0	0	0	0	0	-	-	0	0	0	0	0	0	0	0	0	0	0	0	0	0
Name	-		ffe_coeff_set1_coeff_post5						-		ffe_coeff_set1_coeff_post4						-		ffe_coeff_set1_coeff_post3						ffe_coeff_set1_coeff_post2
Access	-		RW/V						-		RW/V						-		RW/V						RW/V

[29:24] RW/V	ffe_coeff_set1_coeff_post5 ffe_coeff_set1_coeff_post5[29:24] set1 ffe post cursor 5 coeff Reset: hex:0x00;
[21:16] RW/V	ffe_coeff_set1_coeff_post4 ffe_coeff_set1_coeff_post4[21:16] set1 ffe post cursor 4 coeff Reset: hex:0x00;
[13:08] RW/V	ffe_coeff_set1_coeff_post3 ffe_coeff_set1_coeff_post3[13:8] set1 ffe post cursor 3 coeff Reset: hex:0x00;
[07:00] RW/V	ffe_coeff_set1_coeff_post2 ffe_coeff_set1_coeff_post2[7:0] set1 ffe post cursor 2 coeff Reset: hex:0x00;

Bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Reset	0	0	0	0	0	0	0	0	-	-	0	0	0	0	0	0	-	-	0	0	0	0	0	0	-	-	0	0	0	0	0	0
Name	ffe_coeff_set1_coeff_post10				ffe_coeff_set1_coeff_post9				-		ffe_coeff_set1_coeff_post8						-		ffe_coeff_set1_coeff_post7						-		ffe_coeff_set1_coeff_post6
Access	RW/V				RW/V				-		RW/V						-		RW/V						-		RW/V

[31:28] RW/V	ffe_coeff_set1_coeff_post10 ffe_coeff_set1_coeff_post10[31:28] set1 ffe post cursor 10 coeff Reset: hex:0x0;
[27:24] RW/V	ffe_coeff_set1_coeff_post9 ffe_coeff_set1_coeff_post9[27:24] set1 ffe post cursor 9 coeff Reset: hex:0x0;
[21:16] RW/V	ffe_coeff_set1_coeff_post8 ffe_coeff_set1_coeff_post8[21:16] set1 ffe post cursor 8 coeff Reset: hex:0x00;
[13:08] RW/V	ffe_coeff_set1_coeff_post7 ffe_coeff_set1_coeff_post7[13:8] set1 ffe post cursor 7 coeff Reset: hex:0x00;
[05:00] RW/V	ffe_coeff_set1_coeff_post6 ffe_coeff_set1_coeff_post6[5:0] set1 ffe post cursor 6 coeff Reset: hex:0x00;

Bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Reset	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
Name	ffe_coeff_set1_bankB_float3				ffe_coeff_set1_bankB_float2				ffe_coeff_set1_bankB_float1				ffe_coeff_set1_bankA_float3				ffe_coeff_set1_bankA_float2				ffe_coeff_set1_bankA_float1				ffe_coeff_set1_coeff_post12				ffe_coeff_set1_coeff_post11
Access	RW/V				RW/V				RW/V				RW/V				RW/V				RW/V				RW/V				RW/V

[31:28] RW/V	ffe_coeff_set1_bankB_float3 ffe_coeff_set1_bankB_float3[31:28] set1 ffe bankB floating 3 coeff Reset: hex:0x0;
[27:24] RW/V	ffe_coeff_set1_bankB_float2 ffe_coeff_set1_bankB_float2[27:24] set1 ffe bankB floating 2 coeff Reset: hex:0x0;
[23:20] RW/V	ffe_coeff_set1_bankB_float1 ffe_coeff_set1_bankB_float1[23:20] set1 ffe bankB floating 1 coeff Reset: hex:0x0;
[19:16] RW/V	ffe_coeff_set1_bankA_float3 ffe_coeff_set1_bankA_float3[19:16] set1 ffe bankA floating 3 coeff Reset: hex:0x0;
[15:12] RW/V	ffe_coeff_set1_bankA_float2 ffe_coeff_set1_bankA_float2[15:12] set1 ffe bankA floating 2 coeff Reset: hex:0x0;
[11:08] RW/V	ffe_coeff_set1_bankA_float1 ffe_coeff_set1_bankA_float1[11:8] set1 ffe bankA floating 1 coeff Reset: hex:0x0;
[07:04] RW/V	ffe_coeff_set1_coeff_post12 ffe_coeff_set1_coeff_post12[7:4] set1 ffe post cursor 12 coeff Reset: hex:0x0;
[03:00] RW/V	ffe_coeff_set1_coeff_post11 ffe_coeff_set1_coeff_post11[3:0] set1 ffe post cursor 11 coeff Reset: hex:0x0;

Bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Reset	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	0	0	0	0	0	0	0	0	0	0
Name	-																				ffe_coeff_set1_bankC_float3				ffe_coeff_set1_bankC_float2				ffe_coeff_set1_bankC_float1
Access	-																				RW/V				RW/V				RW/V

Bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Reset	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	-	-	0	0	0	0	0	0	-	-	0	0	0	0	0	0
Name	ffe_coeff_set2_coeff_post1								ffe_coeff_set2_coeff_pre1								-		ffe_coeff_set2_coeff_pre2						-		ffe_coeff_set2_coeff_pre3
Access	RW/V								RW/V								-		RW/V						-		RW/V

[31:24] RW/V	ffe_coeff_set2_coeff_post1 ffe_coeff_set2_coeff_post1[31:24] set2 ffe post cursor 1 coeff Reset: hex:0x00;
[23:16] RW/V	ffe_coeff_set2_coeff_pre1 ffe_coeff_set2_coeff_pre1[23:16] set2 ffe pre cursor 1 coeff Reset: hex:0x00;
[13:08] RW/V	ffe_coeff_set2_coeff_pre2 ffe_coeff_set2_coeff_pre2[13:8] set2 ffe pre cursor 2 coeff Reset: hex:0x00;
[05:00] RW/V	ffe_coeff_set2_coeff_pre3 ffe_coeff_set2_coeff_pre3[5:0] set2 ffe pre cursor 3 coeff Reset: hex:0x00;

Bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Reset	-	-	0	0	0	0	0	0	-	-	0	0	0	0	0	0	-	-	0	0	0	0	0	0	0	0	0	0	0	0	0	0
Name	-		ffe_coeff_set2_coeff_post5						-		ffe_coeff_set2_coeff_post4						-		ffe_coeff_set2_coeff_post3						ffe_coeff_set2_coeff_post2
Access	-		RW/V						-		RW/V						-		RW/V						RW/V

[29:24] RW/V	ffe_coeff_set2_coeff_post5 ffe_coeff_set2_coeff_post5[29:24] set2 ffe post cursor 5 coeff Reset: hex:0x00;
[21:16] RW/V	ffe_coeff_set2_coeff_post4 ffe_coeff_set2_coeff_post4[21:16] set2 ffe post cursor 4 coeff Reset: hex:0x00;
[13:08] RW/V	ffe_coeff_set2_coeff_post3 ffe_coeff_set2_coeff_post3[13:8] set2 ffe post cursor 3 coeff Reset: hex:0x00;
[07:00] RW/V	ffe_coeff_set2_coeff_post2 ffe_coeff_set2_coeff_post2[7:0] set2 ffe post cursor 2 coeff Reset: hex:0x00;

Bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Reset	0	0	0	0	0	0	0	0	-	-	0	0	0	0	0	0	-	-	0	0	0	0	0	0	-	-	0	0	0	0	0	0
Name	ffe_coeff_set2_coeff_post10				ffe_coeff_set2_coeff_post9				-		ffe_coeff_set2_coeff_post8						-		ffe_coeff_set2_coeff_post7						-		ffe_coeff_set2_coeff_post6
Access	RW/V				RW/V				-		RW/V						-		RW/V						-		RW/V

[31:28] RW/V	ffe_coeff_set2_coeff_post10 ffe_coeff_set2_coeff_post10[31:28] set2 ffe post cursor 10 coeff Reset: hex:0x0;
[27:24] RW/V	ffe_coeff_set2_coeff_post9 ffe_coeff_set2_coeff_post9[27:24] set2 ffe post cursor 9 coeff Reset: hex:0x0;
[21:16] RW/V	ffe_coeff_set2_coeff_post8 ffe_coeff_set2_coeff_post8[21:16] set2 ffe post cursor 8 coeff Reset: hex:0x00;
[13:08] RW/V	ffe_coeff_set2_coeff_post7 ffe_coeff_set2_coeff_post7[13:8] set2 ffe post cursor 7 coeff Reset: hex:0x00;
[05:00] RW/V	ffe_coeff_set2_coeff_post6 ffe_coeff_set2_coeff_post6[5:0] set2 ffe post cursor 6 coeff Reset: hex:0x00;

Bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Reset	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
Name	ffe_coeff_set2_bankB_float3				ffe_coeff_set2_bankB_float2				ffe_coeff_set2_bankB_float1				ffe_coeff_set2_bankA_float3				ffe_coeff_set2_bankA_float2				ffe_coeff_set2_bankA_float1				ffe_coeff_set2_coeff_post12				ffe_coeff_set2_coeff_post11
Access	RW/V				RW/V				RW/V				RW/V				RW/V				RW/V				RW/V				RW/V

[31:28] RW/V	ffe_coeff_set2_bankB_float3 ffe_coeff_set2_bankB_float3[31:28] set2 ffe bankB floating 3 coeff Reset: hex:0x0;
[27:24] RW/V	ffe_coeff_set2_bankB_float2 ffe_coeff_set2_bankB_float2[27:24] set2 ffe bankB floating 2 coeff Reset: hex:0x0;
[23:20] RW/V	ffe_coeff_set2_bankB_float1 ffe_coeff_set2_bankB_float1[23:20] set2 ffe bankB floating 1 coeff Reset: hex:0x0;
[19:16] RW/V	ffe_coeff_set2_bankA_float3 ffe_coeff_set2_bankA_float3[19:16] set2 ffe bankA floating 3 coeff Reset: hex:0x0;
[15:12] RW/V	ffe_coeff_set2_bankA_float2 ffe_coeff_set2_bankA_float2[15:12] set2 ffe bankA floating 2 coeff Reset: hex:0x0;
[11:08] RW/V	ffe_coeff_set2_bankA_float1 ffe_coeff_set2_bankA_float1[11:8] set2 ffe bankA floating 1 coeff Reset: hex:0x0;
[07:04] RW/V	ffe_coeff_set2_coeff_post12 ffe_coeff_set2_coeff_post12[7:4] set2 ffe post cursor 12 coeff Reset: hex:0x0;
[03:00] RW/V	ffe_coeff_set2_coeff_post11 ffe_coeff_set2_coeff_post11[3:0] set2 ffe post cursor 11 coeff Reset: hex:0x0;

Bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Reset	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	0	0	0	0	0	0	0	0	0	0
Name	-																				ffe_coeff_set2_bankC_float3				ffe_coeff_set2_bankC_float2				ffe_coeff_set2_bankC_float1
Access	-																				RW/V				RW/V				RW/V

Bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Reset	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	-	-	0	0	0	0	0	0	-	-	0	0	0	0	0	0
Name	ffe_coeff_set3_coeff_post1								ffe_coeff_set3_coeff_pre1								-		ffe_coeff_set3_coeff_pre2						-		ffe_coeff_set3_coeff_pre3
Access	RW/V								RW/V								-		RW/V						-		RW/V

[31:24] RW/V	ffe_coeff_set3_coeff_post1 ffe_coeff_set3_coeff_post1[31:24] set3 ffe post cursor 1 coeff Reset: hex:0x00;
[23:16] RW/V	ffe_coeff_set3_coeff_pre1 ffe_coeff_set3_coeff_pre1[23:16] set3 ffe pre cursor 1 coeff Reset: hex:0x00;
[13:08] RW/V	ffe_coeff_set3_coeff_pre2 ffe_coeff_set3_coeff_pre2[13:8] set3 ffe pre cursor 2 coeff Reset: hex:0x00;
[05:00] RW/V	ffe_coeff_set3_coeff_pre3 ffe_coeff_set3_coeff_pre3[5:0] set3 ffe pre cursor 3 coeff Reset: hex:0x00;

Bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Reset	-	-	0	0	0	0	0	0	-	-	0	0	0	0	0	0	-	-	0	0	0	0	0	0	0	0	0	0	0	0	0	0
Name	-		ffe_coeff_set3_coeff_post5						-		ffe_coeff_set3_coeff_post4						-		ffe_coeff_set3_coeff_post3						ffe_coeff_set3_coeff_post2
Access	-		RW/V						-		RW/V						-		RW/V						RW/V

[29:24] RW/V	ffe_coeff_set3_coeff_post5 ffe_coeff_set3_coeff_post5[29:24] set3 ffe post cursor 5 coeff Reset: hex:0x00;
[21:16] RW/V	ffe_coeff_set3_coeff_post4 ffe_coeff_set3_coeff_post4[21:16] set3 ffe post cursor 4 coeff Reset: hex:0x00;
[13:08] RW/V	ffe_coeff_set3_coeff_post3 ffe_coeff_set3_coeff_post3[13:8] set3 ffe post cursor 3 coeff Reset: hex:0x00;
[07:00] RW/V	ffe_coeff_set3_coeff_post2 ffe_coeff_set3_coeff_post2[7:0] set3 ffe post cursor 2 coeff Reset: hex:0x00;

Bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Reset	0	0	0	0	0	0	0	0	-	-	0	0	0	0	0	0	-	-	0	0	0	0	0	0	-	-	0	0	0	0	0	0
Name	ffe_coeff_set3_coeff_post10				ffe_coeff_set3_coeff_post9				-		ffe_coeff_set3_coeff_post8						-		ffe_coeff_set3_coeff_post7						-		ffe_coeff_set3_coeff_post6
Access	RW/V				RW/V				-		RW/V						-		RW/V						-		RW/V